Components / Memory
S-R Flip-Flop in Logisim
Clocked Set-Reset (S-R) Flip-Flop in Logisim: complete characteristic and excitation truth table (Hold, Reset, Set, and 1,1 state), rising-edge CLK triggering, and asynchronous RST pin.
| Library | Memory |
|---|---|
| Type name | S-R Flip-Flop |
| Pins and defaults | j S (-40, 0), clk CLK (-40, 10), k R (-40, 20), rst RST (-20, 30), q Q (0, 0), qn ~Q (0, 20) |
How the S-R Flip-Flop Works in Logisim
The S-R Flip-Flop (Set-Reset Flip-Flop) in Logisim is a clocked, rising-edge triggered 1-bit memory element with Set (S) and Reset (R) control inputs. Unlike an unclocked NOR or NAND S-R latch that reacts immediately whenever its inputs change, the S-R Flip-Flop samples S and R only at the instant the Clock pin (CLK) transitions from Low to High (0 → 1 rising edge).
On a rising clock edge (0 → 1): when S = 0 and R = 0, the flip-flop holds its previous state Q; when S = 0 and R = 1, it resets Q to 0 (~Q = 1); and when S = 1 and R = 0, it sets Q to 1 (~Q = 0). In textbook Boolean design, driving both S = 1 and R = 1 simultaneously is the Invalid / Forbidden input combination because Set and Reset conflict (in Logisim Revisited’s deterministic simulator, S = 1, R = 1 leaves the stored bit unchanged rather than crashing the simulation, but you should avoid S = R = 1 in synchronous designs).
Asynchronous Reset (RST) pin: The bottom pin (rst, at offset -20, 30) is an asynchronous active-high clear input. Driving RST = 1 forces Q = 0 and ~Q = 1 immediately without waiting for a clock edge. Leave RST = 0 (or tied to Ground) during normal clocked operation.
S-R Flip-Flop vs. J-K Flip-Flop: The J-K Flip-Flop has the exact same pin layout (J in place of S, K in place of R) and identical behavior for (0,0), (0,1), and (1,0), but resolves the invalid (1,1) combination by toggling Q (~Q) on each rising clock edge. See our interactive J-K Flip-Flop circuit guide to test both side by side.
Tip: If your state machine ever needs both inputs High (1, 1) to toggle the output, replace the S-R Flip-Flop with a J-K Flip-Flop—their pin locations are identical so your existing wires will snap right in.
S-R Flip-Flop Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| j (S) | Input (Top-left) | 1 bit | Offset (-40, 0). Synchronous Set input: S=1, R=0 sets Q=1 on the rising edge of CLK. |
| clk (CLK) | Input (Middle-left, triangle) | 1 bit | Offset (-40, 10). Rising-edge (0 → 1) clock trigger input. |
| k (R) | Input (Bottom-left) | 1 bit | Offset (-40, 20). Synchronous Reset input: S=0, R=1 clears Q=0 on the rising edge of CLK. |
| rst (RST) | Input (Bottom edge) | 1 bit | Offset (-20, 30). Asynchronous active-high Reset: immediately clears Q=0 when RST=1. |
| q (Q) | Output (Upper-right) | 1 bit | Offset (0, 0). Primary stored state output Q. |
| qn (~Q) | Output (Lower-right) | 1 bit | Offset (0, 20). Complementary state output ~Q. |
S-R Flip-Flop Truth Table & Behavior
| CLK | S (Set) | R (Reset) | Q(next) | ~Q(next) | Effect |
|---|---|---|---|---|---|
| ↑ (0 → 1) | 0 | 0 | Q | ~Q | Hold (retain previous state) |
| ↑ (0 → 1) | 0 | 1 | 0 | 1 | Reset (clear Q to 0) |
| ↑ (0 → 1) | 1 | 0 | 1 | 0 | Set (set Q to 1) |
| ↑ (0 → 1) | 1 | 1 | Invalid / Forbidden | Invalid | Forbidden in S-R design (use J-K Flip-Flop to toggle on 1,1) |
| Any (RST = 1) | X | X | 0 | 1 | Asynchronous Reset (overrides CLK, S, and R) |