Components / Gates
NOR Logic Gate in Logisim
Universal inverted-OR gate (Y = ~(A + B)) that outputs 1 only when all active inputs are 0, and outputs 0 if any input is 1.
| Library | Gates |
|---|---|
| Type name | NOR Gate |
| Pins and defaults | in0..inN (-50, ±10), out0 (0, 0), width 1..32, inputs 2..8 |
How the NOR Works in Logisim
The NOR Gate is an OR gate followed by an inversion bubble (Y = ~(A + B)). It outputs High (1) only when every active input is Low (0); if any input is High (1), its output is immediately forced Low (0).
Like NAND, the NOR Gate is functionally complete (universal). Cross-coupling two NOR gates so each gate’s output feeds the other’s input creates the classic active-high S-R latch, the foundational building block of static memory.
Tip: A multi-input NOR gate is the cleanest way to build a Zero flag detector for an ALU: its output is 1 only when every bit of the result is 0.
NOR Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| in0 .. in(N-1) | Input (Left edge) | 1–32 bits | Located at x = -50. Configurable from 2 to 8 inputs. |
| out0 (out) | Output (Right tip) | 1–32 bits | Located at (0, 0). Outputs ~(in0 + in1 + ...). |
NOR Truth Table & Behavior
| A | B | Y = ~(A + B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |