Components / Gates
NAND Logic Gate in Logisim
Universal inverted-AND gate (Y = ~(A · B)) that outputs 0 only when all active inputs are 1, and outputs 1 if any input is 0.
| Library | Gates |
|---|---|
| Type name | NAND Gate |
| Pins and defaults | in0..inN (-50, ±10), out0 (0, 0), width 1..32, inputs 2..8 |
How the NAND Works in Logisim
The NAND Gate is an AND gate followed by an inverter bubble: it outputs Low (0) only when all active inputs are High (1), and outputs High (1) whenever at least one input is Low (0).
NAND is a universal gate—any Boolean function, combinational circuit, or sequential latch can be constructed exclusively from NAND gates. Tying both inputs of a 2-input NAND gate together (or driving one input with 1) turns it into a NOT gate; two cross-coupled NAND gates form an active-low S-R latch.
Tip: By De Morgan's law, a two-level AND-OR Sum-of-Products circuit converts directly into a two-level NAND-NAND circuit with identical logic.
NAND Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| in0 .. in(N-1) | Input (Left edge) | 1–32 bits | Located at x = -50. Configurable from 2 to 8 inputs. |
| out0 (out) | Output (Right tip) | 1–32 bits | Located at (0, 0). Outputs ~(in0 · in1 · ...). |
NAND Truth Table & Behavior
| A | B | Y = ~(A · B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |