Components / Memory
Register Component in Logisim
Stores an N-bit multi-bit word from input D onto output Q on the rising Clock edge whenever Enable (EN) is High (1).
| Library | Memory |
|---|---|
| Type name | Register |
| Pins and defaults | d D (-40, 0), en EN (-40, 10), clk CLK (-20, 20), rst RST (-10, 20), q Q (0, 0), width 4 (1..32) |
How the Register Works in Logisim
A Register packs N parallel D Flip-Flops (default width = 4 bits, configurable up to 32 bits) into a single component with shared Clock (CLK), Enable (EN), and asynchronous Reset (RST) control pins.
On each rising edge (0 → 1) of CLK, if the Enable input (EN) is 1 (or left unconnected/floating Z, which defaults to enabled), the Register captures the N-bit value on D and drives it onto output Q. When EN = 0, rising clock edges are ignored and Q retains its stored value. Driving RST = 1 asynchronously clears Q to 0 across all bits.
Tip: Wire a Register’s Q output into one input of an Adder and route the Adder’s Sum back to D to build an accumulator register.
Register Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| d (D) | Input (Upper-left) | 1–32 bits (default 4) | Offset (-40, 0). Parallel N-bit data input bus. |
| en (EN) | Input (Lower-left) | 1 bit | Offset (-40, 10). Write Enable (1 or unconnected Z enables loading on rising CLK; 0 holds Q). |
| clk (CLK) | Input (Bottom-left) | 1 bit | Offset (-20, 20). Rising-edge (0 → 1) clock input. |
| rst (RST) | Input (Bottom-right) | 1 bit | Offset (-10, 20). Asynchronous active-high reset (clears stored value to 0). |
| q (Q) | Output (Right edge) | 1–32 bits (default 4) | Offset (0, 0). Stored N-bit output word. |
Register Truth Table & Behavior
| RST | CLK | EN (Enable) | Q(next) |
|---|---|---|---|
| 1 | X | X | 0 (all bits cleared immediately) |
| 0 | ↑ (0 → 1) | 0 | Q (hold current stored word) |
| 0 | ↑ (0 → 1) | 1 (or Z) | D (load new N-bit word from D) |
| 0 | 0, 1, or ↓ | X | Q (hold current stored word) |