Components / Gates
Even Parity Gate in Logisim
IEEE rectangular parity box (labeled 2k) that outputs 1 when an even number of active inputs (0, 2, 4, ...) are High (1).
| Library | Gates |
|---|---|
| Type name | Even Parity |
| Pins and defaults | in0..inN (-50, ±10), out0 (0, 0), width 1..32, inputs 3 (2..8) |
How the Even Parity Works in Logisim
The Even Parity gate (drawn as a square IEEE symbol labeled 2k with 3 inputs by default) outputs High (1) whenever an even number of its active inputs—including zero inputs—are High (1).
It computes the logical complement of the Odd Parity gate, equivalent to an XNOR reduction across all connected inputs. If any active input is Error (E) or all inputs are floating (Z), the gate outputs E.
Tip: Use an Even Parity gate at the receiver end of a communication link to verify that the data bits plus the parity bit contain an even number of 1s.
Even Parity Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| in0 .. in(N-1) | Input (Left edge) | 1–32 bits | Located at x = -50 (default 3 inputs). Configurable from 2 to 8 inputs. |
| out0 (out) | Output (Right edge) | 1–32 bits | Located at (0, 0). Outputs 1 when an even number of active inputs are 1. |
Even Parity Truth Table & Behavior
| in0 | in1 | in2 | Number of 1s | Output (out0) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 (even) | 1 |
| 0 | 0 | 1 | 1 (odd) | 0 |
| 0 | 1 | 1 | 2 (even) | 1 |
| 1 | 1 | 1 | 3 (odd) | 0 |