Circuits / Sequential
S-R Flip-Flop
Sets Q = 1 when S = 1 and resets Q = 0 when R = 1 on a rising clock edge, while S = R = 0 holds the stored bit.
The S-R (Set-Reset) Flip-Flop is a clocked 1-bit sequential memory element with Set (S), Clock (CLK), and Reset (R) inputs.
Unlike an unclocked latch that reacts immediately whenever its inputs change, the clocked S-R Flip-Flop samples S and R only at the rising edge of CLK (when the clock transitions from 0 to 1).
On a rising clock edge: S = 0, R = 0 holds the current state Q; S = 1, R = 0 sets Q to 1 (and NotQ to 0); S = 0, R = 1 resets Q to 0 (and NotQ to 1).
Driving both S = 1 and R = 1 at the same time is the forbidden (invalid) state in S-R design because Set and Reset conflict. A J-K Flip-Flop resolves that conflict by toggling Q when both inputs are 1.
Tip: Avoid driving S = 1 and R = 1 simultaneously. Open the circuit in the simulator, poke S and R, and click Tick to step through Set, Hold, and Reset.