Circuits / Sequential
D Flip-Flop
Captures the data bit on D at the rising edge of the clock and holds it steady on Q until the next rising edge.
The D (Data or Delay) Flip-Flop is the fundamental building block of CPU registers, shift registers, and synchronous state machines.
Its characteristic equation is simply Q(next) = D at the rising edge (0 → 1 transition) of Clock (CLK). Whatever 0 or 1 bit sits on D at the moment CLK rises is captured onto Q, while NotQ outputs the complement.
Between rising clock edges, Q is completely isolated from D: you can toggle D back and forth without disturbing the stored output until the next 0 → 1 clock edge arrives.
Grouping four or eight D Flip-Flops on a shared clock line forms a parallel multi-bit Register.
Tip: Poke D to change the input data bit, then click Tick until CLK transitions from 0 to 1 to watch Q capture the new value.